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Lean Directions
   
Lean Directions June 2009 Issue (Medical manufacturing's prescription for success)

Medical manufacturing's prescription for success

When medical-device manufacturers launch efforts to cut manufacturing costs associated with existing products, they must often do so without undergoing redesigns. The reason: by the time a medical product is outsourced, it has completed its Food & Drug Administration (FDA) approval cycle, making even simple design for manufacturability or testability (DFM/DFT) changes difficult.

The incorporation of lean manufacturing principles as practiced by EPIC Technologies, a Norwalk, Ohio-based electronics manufacturing services provider, is proving to be an effective means for meeting this industry-specific manufacturing challenge.

"We're applying Advanced Product Quality Planning (APQP) techniques developed by the automotive industry," says Ryan Wooten, engineering manager. "These include development of customer required processes through dedication of internal Customer Focus Teams (CFT); utilization of pre-build DFx analysis for manufacturability and testability; reliability laboratory analysis during new product process validation stages; and a focused product launch process with feedback, assessment and corrective action mechanisms to ensure that product meets customer requirements."

Wooten says, "The first step in this process is the design review summary, listing the recommendations of the DFM evaluation with one to five points assigned to each according to level of urgency. For example, if a product has a serious design issue, it receives five points and will not be built, but this is rare. The lesser the design issue, the lesser the point score. For example, if there are issues that 'probably' should be corrected, but aren't really major, three points would be scored. And, in cases where it might be 'nice to have' certain design features that aren't 'critical,' one point would be scored.

"This ranking system helps us to focus our DFM and DFT recommendations in a cost-benefit framework and prioritize discussions on the critical recommendations," Wooten continues. "The company's internal DFM and DFT guidelines are based on industry-accepted guidelines, which are based on those published by IPC (a global trade association for the electronics interconnect industry) and enhanced through production experience and validations. Customer design teams are provided with these guidelines early in the process to stimulate open communication."

Out with the waste

EPIC's efforts to eliminate non-value added activities include the following:
  • Minimize the number of process steps and standardize processes.


  • Maximize processing efficiency using 100 percent surface mount technology (SMT) or 100 percent through-hole assemblies as they are the most efficient to process.


  • Eliminate areas and design elements that increase processing and handling. For example, placing mixed technology on both sides of the board can drive extra automated and manual processing time while increasing handling or thermal-shock-related defects.


  • Reduce changeover time. Standardized panelization reduces printed circuit board (PCB) cost and minimizes setup.


  • Avoid rework by paying attention to layout details.


  • Eliminate unacceptable solder joints caused by improperly sized through-hole pads and holes.


  • Avoid poorly placed fiducials as they impact the accuracy of SMT component layout.


  • Pay attention to orientation of bottom side SMT components as incorrect orientation or incorrect SMT land patterns can cause opens, shorts and other defects.


  • Consider labor or special processing costs in component specification strategy.


  • Specify stainless steel component fastening hardware, which can be exposed on the bottom side of a printed circuit board assembly (PCBA). Conversely, zinc-plated hardware attracts solder and requires masking.


  • Use standardized test platforms to achieve maximum efficiency.


  • Provide automated in-circuit testing (ICT), which offers a more robust and lower cost test than a custom functional tester.


  • Design products to IPC guidelines and have good access points.

Reliability testing is team effort

EPIC'S reliability lab is co-managed by quality and engineering to ensure that there is agreement on support provided. A process engineer, trained in reliability lab processes, runs the lab. Data is collected in production per lab request; appropriate analysis is performed in the lab; reports are generated; appropriate stakeholder reviews are performed; and corrective actions are implemented. The lab focuses on three key areas: new process definition and validation, project launch and quality issue resolution.

Defects often occur as the result of supplier or customer issues rather than in the contractor's process, making quality resolution especially important. Understanding defect risks driven by final assembly processes or end-market applications is critical. For example, as boards become more densely populated, ball grid arrays (BGAs) are in wide use. If the PCBA is flexed too much in the box-build assembly process, stress fractures may occur that ultimately drive hard-to-identify field failures. The faster these issues are identified and corrected, the lower the cost impact on the product launch.

The reliability lab originally addressed these issues as defects occurred. As PCBA complexity increased, the group started offering a package of services to better validate process robustness at both the lab and at customers' operations as part of the new product introduction process.

Susan Mucha

About the author

Susan Mucha is founder of Powell-Mucha Consulting in El Paso, Texas. She has more than 20 years of experience in the electronics manufacturing services (EMS) industry.



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